Computer architectures differ in their method of storing a sequence of bytes in computer memory. Each byte traditionally carries 8 bits of information. To store and process larger numbers, for example, 16-bit or 32-bit quantities, microprocessors store a sequence of bytes in a string together to produce the desired size.
The two most common methods of storing these multi-byte sequences are termed “big-endian” and “little-endian.” In a big-endian computer, the most significant value in the sequence is stored first. In a little-endian computer, the least significant value is stored first. The least significant value is the byte of the sequence that is the smallest. For example, given the two-byte hexadecimal number 4F52, the least significant byte is the “52” byte.
By “first” it is meant the lowest storage address. For example, given the two-byte hexadecimal number 4F52, a big-endian computer would store this number in memory as 4F52. If, for example, the “4F” byte was stored at memory address 1000, the “52” byte would be stored at memory address 1001. Conversely, in a little-endian computer, this number would be stored as 524F, with the “52” byte stored at memory address 1000 and the “4F” byte stored at memory address 1001.
By way of example, IBM's 370 series of computers, many reduced instruction set chip (RISC) based computers and Motorola® microprocessors are big-endian. Intel® microprocessors and the former Digital Equipment Corporation (now Compaq Computer Corporation) Alpha® microprocessor are little-endian.
In both big and little-endian computers, the bits within each byte are traditionally stored in a big-endian format. While it is possible to have a little-endian bit order, most known central processing units and microprocessors are currently designed for a big-endian bit order.
The endianness of a particular computer is relevant when it is exchanging particular types of data with a computer of a differing endianness. By “endianness” it is meant the byte order that a particular computer, file server or network device utilizes, for example big or little-endian. The term “endian neutral” as used herein means a byte order that is defined so that the data stored in an endian neutral data packet can be successfully read by computers of varying endianness. For example, a byte is endian neutral by definition as both big-endian and little-endian computers will properly read the data. Most data transfer protocols and file formats have a set endianness for use with the computer performing any translations as needed.
One example of this is the use of remote direct memory access (RDMA) through certain communication links such as a virtual interface (VI) connection. RDMA is a form of direct memory access, where data is moved directly from a memory location on a first computer to a memory location on a second computer without significant intervention by processes of the central processing unit of either computer. Virtual interface (VI) is a standard for an architecture for connecting between high performance network hardware and computer systems. The VI architecture is defined in Virtual Interface Architecture Specification, Version 1.0, published by a collaboration between Compaq Computer Corp., Intel Corp., and Microsoft Corp., which is hereby incorporated by reference.
To use the RDMA read/write capabilities implemented under the VI architecture, the source computer must supply to the VI interface the source address of the data to be transferred and the destination address on the remote computer for the data. Under the VI architecture, this remote address must be specified in the proper endianness of the remote computer. This requirement allows the remote computer to simply use the received address as a memory address on the remote machine without further processing. In a homogenous networking environment, where all computers involved share the same endianness, this requirement is easily met. However, a need arises to determine the proper endianness of the computer to which a given computer is connected when all computers in a given network do not share the same endianness.